Lattice Semiconductor
Convolutional Encoder User’s Guide
Signal Descriptions
The top-level representation of the Convolutional Encoder is shown in Figure 5. Table 1 contains the signal descrip-
tions. Timing diagrams for the signals are shown in the Timing Diagrams section.
Figure 5. Convolutional Encoder Top Level Block Diagram
clk
dout_valid
Table 1. Core Signals
reset_b
din_valid
din
Convolutional
Encoder
pd_start
rfi
dout
Port
clk
reset_b
din_valid
Bits
1
1
1
I/O
Input
Input
Input
Description
System clock. The clock speed is equal to the input symbol rate.
System-wide asynchronous reset signal, active low.
Denotes valid data is being presented at the encoder input. Must be
asserted only if the output rfi is high.
din
1
Input
Input data to the encoder. Must be presented only if the encoder output
rfi is high.
dout_valid
pd_start
rfi
dout
1
1
1
2 to 8
(non-punctured)
Output
Output
Output
1
(punctured)
Denotes valid data is present at the encoder output.
Signi?es the start of a punctured block.
Indicates the encoder is ready for input.
Output data of the encoder. The data is valid only if the signal
dout_valid is high.
Interfacing the Convolutional Encoder Core
The puncturing-enabled convolutional encoder is a multi-rate system, with the output rate greater than the input
rate. The actual output data rate is dependent on the puncturing rate. The data rate mismatch between input and
output is addressed by the output signal rfi (ready for input). The driving system should not apply an input to the
encoder if the rfi output is low (if this is done, the data will be ignored until rfi is high). When valid data is
applied at the input din, input din_valid must be asserted high. Even if the rfi output is high, the driving sys-
tem can black-out the input by pulling din_valid low. The core will optimize throughput by utilizing any user-
asserted black-out cycles as wait cycles used for data-rate matching.
The output signal pd_start is asserted high to coincide with the start of a punctured block. This signal can be
used to synchronize the Viterbi decoder when decoding the encoded stream.
The output control signal dout_valid is high whenever the output is valid. This can be used as an enable signal
to latch the output to a memory.
Convolutional Encoder Con?guration Options
Con?gurable Parameters
The following core parameters give the user the capability to tailor the core to realize different Convolutional
Encoder con?gurations. These parameters can be con?gured through the GUI dialog box in IPexpress?.
Constraint Length: This de?nes the constraint register length. The value can be any integer from 3 to 12.
Input Rate: This de?nes the input symbol rate for the encoder. The input rate for non-punctured codes is always 1.
For punctured codes, the input rate can be any value from 2 to 12.
4
相关PDF资料
CORE10/100-AR IP CORE10/100 UNLIMITED RTL
CORE1553BBC-AR IP MODULE CORE1553 BUS CTLR
CORE1553BRT-AR IP MODULE CORE1553 REMOTE TERM
CORE8051-AR IP MODULE CORE8051
COREFFT-RM IP MODULE COREFFT
COREFIR-RM IP MODULE COREFIR
COREPCIF-RM IP MODULE COREPCIF
COREU1LL-AR IP MODULE COREU1LL
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